KPIT Interview Questions

The selection procedure for KPIT job is done in the following steps:

1. Written test
2. Technical interview
3. HR round

Written test

• Few aptitude questions
• Technical questions on microcontroller, digital electronics, analog electronic - opams, CMOS,etc.
• C language questions

Technical Round Questions

1. Draw full wave rectifier circuit. Which is better bridge rectifier or centre tapped? 
2. How to verify the health of the 1kb RAM without using checksum.
3. Write a code for moving average when the input is analog data.
4. Draw a memory map for accessing external ROM and write a code to access the external ROM.
5. Design a mod3 counter asynchronous.
6. Transfer characteristics of a clipper was given and told to design the circuit.
7. Draw the output waveform for a RC (also RL) circuit with a step input taking the outputs across R and C separately.
8. More emphasis on projects :
• If you have used a microcontroller you should justify why you have chosen that microcontroller and not any other.
• How do you interface IR sensor to a microcontroller.
• Block diagrams and in depth understanding of each blocks.

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

>

HR round: (To read more about HR questions in other tech companies read here)

1. Tell me about yourself and your family.
2. Why should KPIT hire you? (Tell 3 strengths with suitable examples to substantiate the same)
3. Why do you want to work for KPIT?
4. Do you have any plans for further studies?
5. What are your achievements in college so far?
6. Do you have any specific questions regarding the job?

This is a book that I highly recommend for anyone to improve on their soft skills. This will not just help in your interviews but also in your day-to-day work.

Carry Skip Adder MTech VLSI and Embedded Systems Semester 1 Lab

module CSA_task(Sum,Cout,A,B,Cin);

output reg [7:0] Sum;
output reg Cout;
input [7:0] A,B;
input Cin;
reg w1;
always @ (A or B or Cin)
begin
CSA_4bit (Sum[3:0],w1,A[3:0],B[3:0],Cin);
CSA_4bit (Sum[7:4],Cout,A[7:4],B[7:4],w1);
end
task CSA_4bit;
output [3:0] sum;
output cout;
input [3:0] a,b;
input cin;
reg [3:0] c,g,p;
reg sel;
begin
c[0]=cin;
sum[0]=a[0]^b[0]^c[0];
g[0]=a[0]&b[0];
p[0]=a[0]|b[0];
c[1]=g[0] | (p[0]&c[0]);
sum[1]=a[1]^b[1]^c[1];
g[1]=a[1]&b[1];
p[1]=a[1]|b[1];
c[2]=g[1] | (p[1]&(g[0] | (p[0]&c[0])));
sum[2]=a[2]^b[2]^c[2];
g[2]=a[2]&b[2];
p[2]=a[2]|b[2];
c[3]=g[2] | (p[2]&(g[1] | (p[1]&(g[0] | (p[0]&c[0])))));
sum[3]=a[3]^b[3]^c[3];
g[3]=a[3]&b[3];
p[3]=a[3]|b[3];
cout=g[3] | (p[3]&(g[2] | (p[2]&(g[1] | (p[1]&(g[0] | (p[0]&c[0])))))));
sel=(p[0]&p[1]&p[2]&p[3]);
if(sel)
cout<=cout;
else
cout<=cin;
end
endtask
endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

Testbench:

module CSA_task_tb;
wire [7:0] Sum;
wire Cout;
reg [7:0] A,B;
reg Cin;
CSA_task CSA1(Sum,Cout,A,B,Cin);
initial
begin
A=8'b00000000;B=8'b00000000;Cin=0;
#100;
A=8'b00001111;B=8'b00001111;Cin=1;
#100;
A=8'b11110000;B=8'b11110000;Cin=0;
#100;
A=8'b11001100;B=8'b11001100;Cin=1;
#100;
A=8'b11001100;B=8'b00110011;Cin=0;
#100;
A=8'b10101010;B=8'b10101010;Cin=1;
#100;
A=8'b10101010;B=8'b01010101;Cin=0;
#100;
A=8'b11111111;B=8'b11111111;Cin=1;
end
endmodule

4-BIT CARRY LOOK AHEAD ADDER MTech VLSI and Embedded Systems Semester 1 Lab

Verilog Code:

//Design Carry look ahead adder using 4

module carry_look_adder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire g0,p0,g1,p1,g2,p2,g3,p3;
wire c1,c2,c3;
assign g0 = a[0] & b[0];
assign p0 = a[0] ^ b[0];
assign sum[0] = a[0] ^ b[0] ^ cin;
assign c1 = g0 | (p0 & cin);
assign g1 = a[1] & b[1];
assign p1 = a[1] ^ b[1];
assign sum[1] = a[1] ^ b[1] ^ c1;
assign c2 = g1 | (p1 & c1);
assign g2 = a[2] & b[2];
assign p2 = a[2] ^ b[2];
assign sum[2] = a[2] ^ b[2] ^ c2;
assign c3 = g2 | (p2 & c2);
assign g3 = a[3] & b[3];
assign p3 = a[3] ^ b[3];
assign sum[3] = a[3] ^ b[3] ^ c3;
assign cout = g3 | (p3 & c3);
endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

Test Bench:

module tb;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire cout;
carry_look_adder R1 (a,b,cin,sum,cout);
initial
begin
a=4'b1100;
b=4'b1100;
cin=0;
#100;
a=4'b1110;
b=4'b1100;
cin=0;
end
initial
$monitor("a=%b,b=%b",a,b);
endmodule

Vedic Multiplier

module vedic( a, b, c );
input [1:0]a;// first input
input [1:0]b;// second input
output [3:0]c;// output
wire [3:0]c;
wire [3:0]temp; // four multiplication operation of bits according to vedic logic

assign c[0]=a[0]&b[0];
assign temp[0]=a[1]& b[0];
assign temp[1]=a[0]& b[1];
assign temp[2]=a[1]& b[1];

// using two half adders

ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);

endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

//code for Half adder
module ha(a, b, sum, carry); // a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=(a & b);
assign sum=a^b;
endmodule

code for traffic light controller

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    09:48:37 12/17/2014
// Design Name:
// Module Name:    traffic
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


// code foe traffic light controller
module traffic_lights;
reg clock, red, amber, green;
parameter on = 1, off = 0, red_tics = 30, amber_tics = 3, green_tics = 20;
initial red = off;
initial amber = off;
initial green = off;

always begin // sequence to control the lights.
red = on; // turn red light on
light(red, red_tics); // and wait.
green = on; // turn green light on
light(green, green_tics); // and wait.
amber = on; // turn amber light on
light(amber, amber_tics); // and wait.
end


task light;
output color;
input [31:0] tics;
begin
repeat (tics) @ (posedge clock);
color = off; // turn light off.
end
endtask


always begin // waveform for the clock.
#10 clock = 0;
#10 clock = 1;
end endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

Array Multiplier 4 bit

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    10:52:33 12/17/2014
// Design Name:
// Module Name:    array
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module array(A,B,p,rst);

input [3:0]A;
input [3:0]B;
output [7:0]p;
input rst;

reg [7:0]sum;
reg [7:0]sum1;
reg [7:0]sum2;
reg [7:0]sum3;


always@*
begin
if(rst)
begin
sum1 <= 8'b0;
sum2 <= 8'b0;
sum3 <= 8'b0;
sum <= 8'b0;
end


else
begin
sum  <= {4'b0,(A[3]&B[0]),A[2]&B[0],A[1]&B[0],(A[0]&B[0])};
sum1 <= {3'b0,(A[3]&B[1]),A[2]&B[1],A[1]&B[1],(A[0]&B[1]),1'b0};
sum2 <= {2'b0,(A[3]&B[2]),A[2]&B[2],A[1]&B[2],(A[0]&B[2]),2'b0};
sum3 <= {1'b0,(A[3]&B[3]),A[2]&B[3],A[1]&B[3],(A[0]&B[3]),3'b0};
end


end

assign p = sum + sum1 + sum2 + sum3;
endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

MTech VLSI and Embedded Systems Semester 1 - 4/8-BIT Adder / Substractor

Sum = A ⊕ B

Carry = AB

Verilog Code

module cra(a,b,cin,sum,cout);
input [7:0] a,b;
input cin;
output [7:0] sum;
output cout;
wire c1,c2,c3,c4,c5,c6,c7;
assign sum[0] = a[0] ^ b[0] ^ cin;
assign c1 = a[0] & b[0] | b[0] & cin | a[0] & cin;
assign sum[1] = a[1] ^ b[1] ^ c1;
assign c2 = a[1] & b[1] | b[1] & c1 | a[1] & c1;
assign sum[2] = a[2] ^ b[2] ^ c2;
assign c3 = a[2] & b[2] | b[2] & c2 | a[2] & c2;
assign sum[3] = a[3] ^ b[3] ^ c3;
assign c4 = a[3] & b[3] | b[3] & c3 | a[3] & c3;
assign sum[4] = a[4] ^ b[4] ^ c4;
assign c5 = a[4] & b[4] | b[4] & c4 | a[4] & c4;
assign sum[5] = a[5] ^ b[5] ^ c5;
assign c6 = a[5] & b[5] | b[5] & c5 | a[5] & c5;
assign sum[6] = a[6] ^ b[6] ^ c6;
assign c7 = a[6] & b[6] | b[6] & c6 | a[6] & c6;
assign sum[7] = a[7] ^ b[7] ^ c7;
assign cout = a[7] & b[7] | b[7] & c7 | a[7] & c7;
endmodule

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation:

Test Bench:

module tb;
reg [7:0] a,b;
reg cin;
wire [7:0] sum;
wire cout;
cra R1 (a,b,cin,sum,cout);
initial
begin
a=8'b0000_0010;
b=8'b0001_0100;
cin=0;
#100;
a=8'b0000_0010;
b=8'b0001_0100;
cin=0;
#100;
a=8'b0000_0010;
b=8'b0011_0100;
cin=0;
#100;
a=8'b0000_0010;
b=8'b0011_0100;
cin=0;
#100;
a=8'b0000_0010;
b=8'b1111_0100;
cin=0;
#100;
a=8'b0000_1111;
b=8'b0000_0100;
cin=0;
#100;
end
endmodule

D flipflop

// code for dff module
Dff(input d,input clk,output reg q);
always @(posedge clk) // note: lines whithin the always block are executed sequententialy
begin
q<=d;
end
endmodule // code ends

This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog

I suggest going through these books for Digital Electronics preparation: