`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:52:33 12/17/2014
// Design Name:
// Module Name: array
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module array(A,B,p,rst);
input [3:0]A;
input [3:0]B;
output [7:0]p;
input rst;
reg [7:0]sum;
reg [7:0]sum1;
reg [7:0]sum2;
reg [7:0]sum3;
always@*
begin
if(rst)
begin
sum1 <= 8'b0;
sum2 <= 8'b0;
sum3 <= 8'b0;
sum <= 8'b0;
end
else
begin
sum <= {4'b0,(A[3]&B[0]),A[2]&B[0],A[1]&B[0],(A[0]&B[0])};
sum1 <= {3'b0,(A[3]&B[1]),A[2]&B[1],A[1]&B[1],(A[0]&B[1]),1'b0};
sum2 <= {2'b0,(A[3]&B[2]),A[2]&B[2],A[1]&B[2],(A[0]&B[2]),2'b0};
sum3 <= {1'b0,(A[3]&B[3]),A[2]&B[3],A[1]&B[3],(A[0]&B[3]),3'b0};
end
end
assign p = sum + sum1 + sum2 + sum3;
endmodule
This is the best book to learn Digital Design using Verilog HDL, VHDL and System Verilog
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:52:33 12/17/2014
// Design Name:
// Module Name: array
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module array(A,B,p,rst);
input [3:0]A;
input [3:0]B;
output [7:0]p;
input rst;
reg [7:0]sum;
reg [7:0]sum1;
reg [7:0]sum2;
reg [7:0]sum3;
always@*
begin
if(rst)
begin
sum1 <= 8'b0;
sum2 <= 8'b0;
sum3 <= 8'b0;
sum <= 8'b0;
end
else
begin
sum <= {4'b0,(A[3]&B[0]),A[2]&B[0],A[1]&B[0],(A[0]&B[0])};
sum1 <= {3'b0,(A[3]&B[1]),A[2]&B[1],A[1]&B[1],(A[0]&B[1]),1'b0};
sum2 <= {2'b0,(A[3]&B[2]),A[2]&B[2],A[1]&B[2],(A[0]&B[2]),2'b0};
sum3 <= {1'b0,(A[3]&B[3]),A[2]&B[3],A[1]&B[3],(A[0]&B[3]),3'b0};
end
end
assign p = sum + sum1 + sum2 + sum3;
endmodule
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