module vedic( a, b, c );
input [1:0]a;// first input
input [1:0]b;// second input
output [3:0]c;// output
wire [3:0]c;
wire [3:0]temp; // four multiplication operation of bits according to vedic logic
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]& b[0];
assign temp[1]=a[0]& b[1];
assign temp[2]=a[1]& b[1];
// using two half adders
ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);
endmodule
//code for Half adder
module ha(a, b, sum, carry); // a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=(a & b);
assign sum=a^b;
endmodule
input [1:0]a;// first input
input [1:0]b;// second input
output [3:0]c;// output
wire [3:0]c;
wire [3:0]temp; // four multiplication operation of bits according to vedic logic
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]& b[0];
assign temp[1]=a[0]& b[1];
assign temp[2]=a[1]& b[1];
// using two half adders
ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);
endmodule
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//code for Half adder
module ha(a, b, sum, carry); // a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=(a & b);
assign sum=a^b;
endmodule
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